1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors in complex circuits including a complex logic circuitry and a memory area, such as a cache memory of a CPU.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions also raises a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the reduction of so-called short channel effects, which occur upon reducing the channel length. Generally, with a reduced channel length, the controllability of the channel becomes increasingly difficult and requires specific design measures, such as reduction of the thickness of the gate insulation layer, increased doping concentrations in the channel regions and the like. These countermeasures may reduce the charge carrier mobility in the channel region. Accordingly, to further increase transistor performance, it has been proposed to increase the charge carrier mobility in the channel region for a given channel length.
In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device and may affect the channel controllability as previously explained, thereby making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed to adjust a desired threshold voltage. Second, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region may increase the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity for N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
Therefore, a technique is frequently used that enables the creation of desired stress conditions within the channel region of different transistor elements by individually modifying the stress characteristics of a contact etch stop layer that is formed after completion of the basic transistor structure in order to form contact openings to the gate and drain and source terminals in an interlayer dielectric material. The effective control of mechanical stress in the channel region, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress in the contact etch stop layer in order to position a contact etch contact layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively in the respective channel regions.
Moreover, other enhanced junction engineering techniques may be used in advanced SOI transistors for enhancing the performance thereof by creating more abrupt junctions for reducing the junction capacitance, which may translate into increased switching speed. To this end, a so-called pre-amorphization step may be performed prior to the drain/source implantation in order to more precisely define the dopant concentration. The substantially amorphous silicon in the drain and source regions requires, however, a re-crystallization anneal, which results in dislocation defects in the body region of the SOI transistor and in the drain and source regions. In SOI architectures, the further reduced junction capacitance in combination with the per se unwanted dislocation defects may result in a significant performance gain, since the increased junction leakage caused by the dislocation defects may reduce floating body effects while the reduced junction capacitance contributes to increased switching speed. Thus, this enhanced junction engineering may be combined with the stress layer approach in an attempt to further increase device performance. Although this technique is highly efficient in individually enhancing the performance of individual transistors, an increased failure probability and/or production yield may be observed in complex circuits comprising logic circuits and high density memory areas, such as static RAM (random access memory) cells, thereby rendering the above technique less desirable for the formation of highly advanced integrated circuits.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.